1. Field
The following description relates to a method of manufacturing a nonvolatile memory device.
2. Description of the Related Art
Nonvolatile memory devices, particularly flash memory devices, are largely classified as Erasable Programmable Read-Only Memory (EPROM) Tunnel Oxide (ETOX) flash memory devices or split gate flash memory devices. ETOX flash memory devices have smaller memory cells than split gate flash memory devices. However, since ETOX flash memory devices require the implantation of carriers at a high temperature when programmed, a program current for ETOX flash memory devices is relatively high, and ETOX flash memory devices are susceptible to frequent program and read errors. In addition, ETOX flash memory devices are not free from over-erase issues.
While split gate flash memory devices have relatively large memory cells, they also have excellent properties. Thus, split gate flash memory devices have been widely used in the field of semiconductor devices. Split gate flash memory devices can eliminate the over-erase problem experienced with ETOX flash memory devices because each unit cell thereof is equipped with a selection transistor that maintains a predetermined threshold voltage that can be detected from the outside even when the cell transistor is depleted.
Various techniques have been employed to manufacture a split gate nonvolatile memory device. Split gate nonvolatile memory devices have been developed to address the over-erase problem associated with typical ETOX nonvolatile memory devices. However, the channel length of selection transistors in a split gate nonvolatile memory device is determined by a photolithography and, thus, may often become irregular due to the limits in the alignment capability of lithography equipment.
To address this problem, a method of fabricating a nonvolatile memory device has been developed that can facilitate the formation of control gate poly spacers and prevent the occurrence of a shadow effect during an ion implantation by using an etch-back, instead of photolithography, to form a cell control gate pattern. This method involves forming a control gate in the form of a spacer by performing an etch-back using the height of a floating gate. However, according to this method, while the control gate can be uniform on the sides of the floating gate, a bias cannot be applied to the control gate.